Fully pipelined real time hardware solution for High Efficiency Video Coding (HEVC) intra prediction

Farouk Amish (1) , El-Bay Bourennane (1)

1 Le2i - Laboratoire Electronique, Informatique et Image [UMR6306]

A fully pipelined hardware accelerator for the High Efficiency Video Coding (HEVC) intra prediction is presented in this paper in order to reduce the computation complexity coming with this module and to accelerate the concerned calculations. Two reconfigurable structures are developed in this paper, the first one concerns angular modes and is identified as Processing Element for Angular (PEA) modes, the other is made in order to handle with the Planar mode and is identified as Processing Element for the Planar (PEP) mode. Each structure is repeated in five paths, that our architecture composed of, working in parallel way. This architecture supports all intra prediction modes for all prediction unit sizes. The synthesis results show that our design can run at 219 MHz for Xilinx Virtex 6 and is capable to process real time 110 1080p frames per second or 24 4K frames per second. (C) 2015 Elsevier B.V. All rights reserved.

Mots clés: HEVC; Intra prediction; Image compression; Reconfigurable computing; Real-time processing; FPGAs

Domaines: Informatique [cs]; Traitement du signal et de l'image [eess.SP]

Farouk Amish, El-Bay Bourennane. Fully pipelined real time hardware solution for High Efficiency Video Coding (HEVC) intra prediction. Journal of Systems Architecture, 2016, 64, pp.133 - 147. ⟨10.1016/j.sysarc.2015.10.002⟩. ⟨hal-01431245⟩