H. Ziegler, M. W. Hall, and P. Diniz, Compiler-generated communication for pipelined FPGA applications, Proceedings of the 40th conference on Design automation , DAC '03, pp.610-615, 2003.
DOI : 10.1145/775832.775986
URL : http://www.cecs.uci.edu/~papers/compendium94-03/papers/2003/dac03/pdffiles/35_3.pdf

J. Cong, Y. Fan, G. Han, W. Jiang, and Z. Zhang, Behavior and communication co-optimization for systems with sequential communication media, Proceedings of the 43rd annual conference on Design automation , DAC '06, pp.43-675, 2006.
DOI : 10.1145/1146909.1147080

P. Li, L. Pouchet, and J. Cong, Throughput optimization for high-level synthesis using resource constraints, IMPACT 2014. Fourth International Workshop on Polyhedral Compilation Techniques. In conjunction with HiPEAC 2014, 2014.
DOI : 10.1145/2684746.2689065

Q. Huang, R. Lian, A. Canis, J. Choi, R. Xi et al., The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware, ACM Transactions on Reconfigurable Technology and Systems, vol.8, issue.3
DOI : 10.2197/ipsjjip.17.242

M. Mehrara, T. Jablin, D. Upton, D. August, K. Hazelwood et al., Multicore compilation strategies and challenges, IEEE Signal Processing Magazine, vol.26, issue.6, pp.55-63, 2009.
DOI : 10.1109/MSP.2009.934117
URL : http://www.cs.virginia.edu/~dsu9w/ieeespm09.pdf

J. H. Ahn, M. Erez, and W. J. Dally, Tradeoff between data-, instruction-, and thread-level parallelism in stream processors, Proceedings of the 21st annual international conference on Supercomputing, ICS '07, pp.126-137, 2007.
DOI : 10.1145/1274971.1274991

. Xilinx, Introduction to fpga design with vivado high-level synthesis, Xilinx, Tech. Rep. UG998 (v1.0), 2013.

W. Zuo, Y. Liang, P. Li, K. Rupnow, D. Chen et al., Improving high level synthesis optimization opportunity through polyhedral transformations, Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays, FPGA '13, pp.9-18, 2013.
DOI : 10.1145/2435264.2435271
URL : http://cadlab.cs.ucla.edu/~cong/papers/fpga13_1.pdf

L. Pouchet and P. , The Polyhedral Compiler Collection., version 1

A. M. Steven-derrien and A. Kumar, S2s4hls-sp1 progress report, INRIA -University of Rennes, vol.1, 2008.

A. Morvan, S. Derrien, and P. Quinton, Efficient nested loop pipelining in high level synthesis using polyhedral bubble insertion, 2011 International Conference on Field-Programmable Technology, pp.1-10, 2011.
DOI : 10.1109/FPT.2011.6132715
URL : https://hal.archives-ouvertes.fr/hal-00746434

M. Alle, A. Morvan, and S. Derrien, Runtime dependency analysis for loop pipelining in high-level synthesis, Proceedings of the 50th Annual Design Automation Conference on, DAC '13, pp.1-10, 2013.
DOI : 10.1145/2463209.2488796
URL : https://hal.archives-ouvertes.fr/hal-00921416

J. Lee, Y. Hsu, and Y. Lin, A new integer linear programming formulation for the scheduling problem in data path synthesis, Computer-Aided Design, 1989.