A templated programmable architecture for highly constrained embedded HD video processing - Archive ouverte HAL Accéder directement au contenu
Article Dans Une Revue Journal of Real-Time Image Processing Année : 2019

A templated programmable architecture for highly constrained embedded HD video processing

(1) , (2) , (3) , (4) , (5)
1
2
3
4
5

Résumé

The implementation of a video reconstruction pipeline is required to improve the quality of images delivered by highly constrained devices. These algorithms require high computing capacities—several dozens of GOPs for real-time HD 1080p video streams. Today’s embedded design constraints impose limitations both in terms of silicon budget and power consumption—usually 2 mm2 for half a Watt. This paper presents the eISP architecture that is able to reach 188 MOPs/mW with 94 GOPs/mm2 and 378 GOPs/mW using TSMC 65-nm integration technology. This fully programmable and modular architecture, is based on an analysis of video-processing algorithms. Synthesizable VHDL is generated taking into account different parameters, which simplify the architecture sizing and characterization.
Fichier non déposé

Dates et versions

hal-01949614 , version 1 (10-12-2018)

Identifiants

Citer

Mathieu Thevenin, Michel Paindavoine, Renaud Schmit, Barthélémy Heyrman, Laurent Letellier. A templated programmable architecture for highly constrained embedded HD video processing. Journal of Real-Time Image Processing, 2019, 16 (1), pp.143-160. ⟨10.1007/s11554-018-0808-6⟩. ⟨hal-01949614⟩
124 Consultations
0 Téléchargements

Altmetric

Partager

Gmail Facebook Twitter LinkedIn More