A templated programmable architecture for highly constrained embedded HD video processing

Mathieu Thevenin (1) , Michel Paindavoine (2) , Renaud Schmit (3) , Barthélémy Heyrman (4) , Laurent Letellier (5)

1 LCAE (CEA, LIST) - Laboratoire Capteurs et Architectures Electroniques (CEA, LIST)
2 LEAD - Laboratoire d'Etude de l'Apprentissage et du Développement [Dijon]
3 DACLE-LIST - Département d'Architectures, Conception et Logiciels Embarqués-LIST
4 Le2i - Laboratoire Electronique, Informatique et Image [UMR6306]
5 LIST (CEA) - Laboratoire d'Intégration des Systèmes et des Technologies

The implementation of a video reconstruction pipeline is required to improve the quality of images delivered by highly constrained devices. These algorithms require high computing capacities—several dozens of GOPs for real-time HD 1080p video streams. Today’s embedded design constraints impose limitations both in terms of silicon budget and power consumption—usually 2 mm2 for half a Watt. This paper presents the eISP architecture that is able to reach 188 MOPs/mW with 94 GOPs/mm2 and 378 GOPs/mW using TSMC 65-nm integration technology. This fully programmable and modular architecture, is based on an analysis of video-processing algorithms. Synthesizable VHDL is generated taking into account different parameters, which simplify the architecture sizing and characterization.

Mots clés: SIMD; VLIW; Programmable; Low silicon footprint; Low-power

Domaines: Architectures Matérielles [cs.AR]; Traitement du signal et de l'image [eess.SP]

Mathieu Thevenin, Michel Paindavoine, Renaud Schmit, Barthélémy Heyrman, Laurent Letellier. A templated programmable architecture for highly constrained embedded HD video processing. Journal of Real-Time Image Processing, 2019, 16 (1), pp.143-160. ⟨10.1007/s11554-018-0808-6⟩. ⟨hal-01949614⟩